PLL control circuits are widely used in radio, telecommunications, computers and other electronic applications. They may generate stable frequencies, recover a signal from a noisy communication channel, or distribute clock timing pulses in digital logic designs such as microprocessors. Traditionally, the PLL circuit has been an analog block, including the basic components of a voltage control oscillator (VCO), phase and frequency detector (PFD), charge pump, low pass filter (LPF) and a feedback path. However, such analog PLL circuits include a number of capacitors that require a significantly large chip area. Additionally these circuits are very sensitive to power noise.
More recently, PLL circuit design has evolved to a greater use of digital control. The first generation digital PLL uses one external high frequency clock to sample the reference clock, then generates the output clock by dividing or multiplying a certain number according to requirement. The frequency of an external clock having accuracy required by such PLL circuits is limited with respect to its capability for applying a sampling rate that can accommodate high frequency reference clock signals. As this design can only be used in low frequency applications, a hybridization of analog and digital elements has been pursued. With such an approach, chip area has not been significantly reduced, while performance is markedly decreased.
A conventional digital PLL includes a digitally controlled oscillator (DCO). A conventional DCO includes a number of delay cells (e.g., buffers) and a number of load cells that are selectively activated and deactivated to control delay of the DCO loop by adjusting the number of delay cells that are active and the number of load cells that are switched on during any particular clock cycle. For example, the frequency of the DCO can be changed by digitally changing either the number of delay cells that are active or by changing the delay cell's loading by changing the number of load cells that are switched on during any particular clock cycle. This allows the DCO to provide two different types of delay adjustment.
A need exists for an improved PLL control system. It would be desirable if such an improved PLL control system can maintain lock status when temperature or supply voltage varies. Such a digital PLL circuit should also encompass a small chip area and exemplify other good performance capabilities. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.